How big are your SVE registers ? (AWS Graviton)

Amazon has some neat ARM-based systems based on Amazon’s own chips (Graviton). You can access them through Amazon’s web services (AWS). These processors have advanced vector instructions able to process many values at once. These instructions are part of an instruction sets called SVE for Scalable Vector Extension. SVE has a trick: it hides its internal register size from you. Thus, to the question “how many values can it process at once?”, the answer is ‘”it depends”.

Thankfully, you can still write a program to find out. The svcntb intrinsic tells you how many 8-bit integers fits in a full register. Thus the following C++ line should tell you the vector register size in bytes:

std::cout << "detected vector register size (SVE): " 
  << svcntb() << " bytes" << std::endl;

And here is what I get currently on an AWS server:

$ ./svesize
detected vector register size (SVE): 32 bytes

It is hard to find ARM processors with such wide registers (32 bytes) and it is unclear whether future iterations will still have 32 bytes registers.

My source code is available.

Daniel Lemire, "How big are your SVE registers ? (AWS Graviton)," in Daniel Lemire's blog, November 29, 2022.

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Daniel Lemire

A computer science professor at the University of Quebec (TELUQ).

5 thoughts on “How big are your SVE registers ? (AWS Graviton)”

  1. Interesting – svlen_* isn’t documented in the current ACLE, but it seems like it may have been in an earlier version. It seems like current GCC/Clang accept it as well.

    Should probably use the documented svcntb() instead though.

    I think Neoverse V1 is the only ARM processor with 256-bit vectors. Neoverse V2 has reverted to 128-bit vectors.

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