1 September 2025 · 3 min
Our processors execute instructions based on a clock. Thus, a 4 GHz processor has 4 billion cycles per second. It is difficult to increase the clock frequency of our processors. If you go much beyond 5 GHz, your processor is likely to overheat or otherwise fail.
So, how do we go faster? Modern processors can execute multiple instructions simultaneously. It is sometimes called superscalar execution. Most processors can handle 4 instructions per cycle or more. A recent Apple processor can easily sustain over 8 instructions per cycle.
However, the number of instructions executed depends on the instructions themselves. There are inexpensive instructions (like additions) and more costly ones (like integer division). The less costly the instructions, the more can be executed per cycle.
A processor has several execution units. With four execution units capable of performing additions, you might execute 4 additions per cycle. More execution units allow more instructions per cycle.
Typically, x86-64 processors (Intel/AMD) can retire at most one multiplication instruction per cycle, making multiplications relatively expensive compared to additions. In contrast, recent Apple processors can retire two multiplications per cycle.
The latest AMD processors (Zen 5) have three execution units capable of performing multiplications, potentially allowing 3 multiplications per cycle in some cases. Based solely on execution units, a Zen 5 processor could theoretically retire 3 additions and 3 multiplications per cycle.
But that is not all. I only counted conventional multiplications on general-purpose 64-bit registers. The Zen 5 has four execution units for 512-bit registers, two of which can perform multiplications. These 512-bit registers allow us to do many multiplications at once, by packing several values in each register.
Generally our general-purpose processors are getting wider: they can retire more instructions per cycle. That is not the only possible design. Indeed, these wider processors require many more transistors. Instead, you could use these transistors to build more processors. And that is what many people expected: they expected that our computers would contain many more general-purpose processors.
A processor design like the AMD Zen 5 is truly remarkable. It is not simply a matter of adding execution units. You have to bring the data to these units, you have to order the computation, handle the branches.
What it means for the programmers is that even when you do not use parallelism explicitly, your code executes in a parallel manner under the hood no matter what.
Daniel Lemire, "Processors are getting wider," in Daniel Lemire's blog, September 1, 2025, https://lemire.me/blog/2025/09/01/processors-are-getting-wider/.
[BibTeX]
Alexander Yee gives some insight about the potential performance of the 3 integer multipliers: https://www.numberworld.org/blogs/2024_8_7_zen5_avx512_teardown/ (close to the bottom of the page).
You are a several years late.
https://hardwaretimes.com/amd-zen-vs-zen-2-vs-zen-3-vs-zen-4-vs-zen-5-core-architecture-road-to-ryzen-9000-cpus/
This game has been played for a long time.
Worked with the Burroughs “Large Systems” (mainframes) in the early 1980s. They had an 80-bit wide path to memory, and scheduled stack-machine byte-codes out of the wide words. From a conversation with a CPU-architect, they were getting parallel execution on their high-end machines.
Seem to recall the published studies hit a practical limit on that sort of look-ahead at the CPU level.
VLIW CPUs were a thing a couple of decades back – lots of small instructions in one word. Notion was to push the instruction scheduling to the compiler. Seem to recall they hit a practical limit on how much could be compile-scheduled in parallel.
If the practical limit on in-CPU parallel is somewhat small, the AMD Zen family might already there. In which case you are better off spending die-space on more CPUs.
We might already be at the practical limit.
A recent perverse fascination of mine is that although I’m a dyed-in-the-wool I’m-greedier-than-though type who wants as many instructions executed per clock as possible, the universe has recently pointed out that at some point, watts per instruction goes through the roof when you play superscalar, superpipelined, superwide dataword games. That combined with the point that hyperthreading (on one honking enormous performance core) doesn’t buy you as much as just having two efficiency cores, means that some more thought by us greedy folks might be in order. Intel’s 15th gen CPUs don’t get much love, but I think they’ve got the right idea, or at least a fair number of reasonably good ideas.
Similarly, in my day (SB ’76), we thought better algorithms and coding were important for improving performance. The compilers designed for supercalar superpipelined machines proved us wrong, for the nonce, but I’d think that your algorithms would need to know that you can do three multiplies at a time to actually get full performance from three multipliers.
Empirically, Apple has the wider cores and they also run very cool.
I’m not that surprised there’s been only one mul per cycle before. First, x86 simply made that impossible for the longest time (MUL and IMUL used fixed registers), so we had to wait for MULX. And even then, the primary target for doing lots of multiplications has to be bignum work, which while important for cryptography rarely seems to be a large chunk of total CPU time.
Of course, floating-point multiplications have been plenty-per-cycle for a long time; even Haswell could start three vector FMAs every cycle. And you could reuse the float multipliers for vectorized 53×53 int muls somewhat more recently. So it’s really the last barrier that’s going down in Zen 5.
It’s interesting that while the Arm cores are getting wider and with higher IPC, this seems to be mostly balanced out by the fact that you just need more Arm instructions to do the same thing. M1 IPC isn’t really comparable to Core/Zen IPC even though the numbers sound impressive.
Please see…
ARM instructions do “less work”?, in Daniel Lemire’s blog, May 12, 2023.